Image Source: www.anraimports.com
Authors: Abhijit Athavale & Pete Gasperini
In the first week of July, an editorial entitled “High Tech White Elephants – The Tragic Mistake of India’s Silicon Foundries” ( http://vigilfuturi.blogspot.com/2014/07/high-tech-white-elephants-tragic.html) argued against New Delhi’s $4.4B USD subsidization of two separate projects to build 22nm and 28nm silicon fabs on Indian soil. The great weakness of the program, of course, is that the fabs are to be constructed at great expense with process technology that would be considered obsolete once the fabs were ready to ramp production. The plan is, in essence, equivalent to building mega-battleships like the Bismarck and Yamato in 1946. The argument cited further faults in the initiative on economic, technological and environmental grounds, calling for New Delhi to instead remove regulatory and labor law impediments on an already flourishing domestic High Tech sector.
In the first week of July, an editorial entitled “High Tech White Elephants – The Tragic Mistake of India’s Silicon Foundries” ( http://vigilfuturi.blogspot.com/2014/07/high-tech-white-elephants-tragic.html) argued against New Delhi’s $4.4B USD subsidization of two separate projects to build 22nm and 28nm silicon fabs on Indian soil. The great weakness of the program, of course, is that the fabs are to be constructed at great expense with process technology that would be considered obsolete once the fabs were ready to ramp production. The plan is, in essence, equivalent to building mega-battleships like the Bismarck and Yamato in 1946. The argument cited further faults in the initiative on economic, technological and environmental grounds, calling for New Delhi to instead remove regulatory and labor law impediments on an already flourishing domestic High Tech sector.
Defenders of the government initiative have brought forth a
new justification for a local source of microchip manufacturing which revolves
around security concerns. Specifically, the issue bears on the possibility of
hardware back doors being surreptitiously embedded in chip designs to
facilitate clandestine infiltration of commercial and military computing &
communications systems deployed in India.
Stolen sweets are always sweeter – Thomas Randolph
The security argument contends that Indian semiconductor
design firms are vulnerable to having their designs tampered with once they
send their design databases overseas for manufacturing. The worry is that designs
could be intercepted by 3rd parties and altered to include circuitry which
would allow a malefactor to access the chip remotely and take control of its
functions. Malicious activity could include deactivating the chip, implanting
viruses, stealing information, monitoring activity or exercising control over
the system.
A notorious example of this is the Actel/MicroSemi ProASIC3
A3P250, which was discovered to have a hardware back door that could be
accessed thru the chip’s JTAG ports:
The programmable logic device in question is widely used in guidance
systems, weaponry and communications systems by the US armed forces. When the story was first released, suspicion
fell on China, as the chip was thought to have been manufactured there. As it
turned out, the product was actually produced in a fab facility in Taiwan and
the back door circuitry was intentionally inserted by the company that designed
the chip. Though on the surface this suggests that the security apprehensions
of India fab supporters are appropriate, the event actually nullifies their
argument.
A system can
be defined as a set of elements standing in interrelations. - Ludwig von Bertalanffy
Chip design is an extraordinarily complex, expensive and
time consuming endeavor. The typical design team requires 30-50 engineers with
years of specialized training & expertise to dedicate themselves for 12-18
months in order to successfully conclude a design – and often enough, those
designs require an extra 6 months of work to fix flaws discovered after product
release. A highly simplified timeline is
offered below.
The
engineering team uses a set of expensive software tools from various EDA
vendors in order to create an ESL model of the design, capture its particulars
in a high level description language, simulate it, analyze signaling &
timing, integrate a clocking scheme, embed test structures, place and route
circuit blocks and otherwise prepare the design database for release to the
backend (manufacturing.) Each stage of
the design has its own methodology which involves testing, verification and
simulation using physical, functional and performance models of increasing
precision. There are feedback loops for each stage and additional loops nested
throughout the design flow. Each stage is of such complexity that there are
engineers on the team who specialize in that particular section and in the use
of specific tools. A highly abridged representation of a typical chip
development flow is illustrated below.
Image Source: Wikipedia
The intricacy of chip design and the knowledge &
expertise required to execute designs successfully cannot be overstated. There
are signal integrity and timing issues that require years of training and
experience even to just comprehend. Interconnecting transistors and circuit
blocks requires a deep understanding of 3D parasitic issues (RCL), which
themselves can only be grasped after extensive training in solid state
physics, electromagnetism, mathematics, circuit design and certain aspects of metallurgy,
materials science, organic & non-organic chemistry. The design itself is very carefully tuned over
PVT (process, voltage, temperature) parameters in order to maximize yield at a
given foundry and process node. These physical design issues are of critical
importance, as overlooking even minor discrepancies can result in false
signaling, lost data, functional faults and yield decline.
One can immediately deduce why it is thus impossible for a
fab to secretly alter a GDSII design database. To put it simply: even a minor
change in one portion of a design will ripple thru the architecture in its
entirety with unpredictable effects. If you tamper with a design and insert
even just 10,000 gates for a simple 32b MCU with no L1 cache, you will disrupt
carefully engineered 3D interconnect schemes, parasitics loads, power
distribution, signaling, clock skew, bus loads, circuit layouts and so forth. You may have to meddle with I/O as well in
order to access the hardware Trojan. This could affect die size, pad layout and
I/O performance, amongst other things.
After changing a design, the entire verification process
will have to be recreated and executed. Functional verification of chip designs
is a profoundly complex and specialized field, as verifying integrated circuits
is a NP-hard problem because of all the possible output combinations of digital
logic. Functionally re-verifying the design requires the saboteur to ensure
that he doesn’t include vital signaling in a vast list of logic don’t-cares
while re-closing timing, verifying chip-wide signal integrity and making
certain that the design is still functionally intact.
You cannot
make a crab walk straight. - Aristophanes
Does this mean that it is impossible to insert a hardware
Trojan into a chip design? No, of course not. The Actel FPGA is incontestable
proof that it can be implemented. However, it is clear that only the original
designers can successfully integrate a hardware backdoor. A clandestine
engineering team, once provided the GDSII database, would have to meticulously
reverse engineer the design and, using the exact same EDA toolset and models,
precisely regenerate the development environment of the original design team.
Such an effort would take years, and since the original chip
would have by that time been released to the market during those intervening
years and been designed into target systems and applications, the sabotaged
chip would have missed its window of opportunity. Thus, the scenario of a
foreign foundry inserting a hardware backdoor into an Indian chip design, successfully manufacturing it and using that backdoor to access Indian-owned systems is delusional and fantastical. It simply cannot
be done.
A Better Path
The previous editorial on this topic has already described a
more productive use of taxpayer funds to drive India’s advancement on the
industrial technology chain – a Manhattan Project devoted to carbon-based
semiconductor technology, using DARPA program management techniques and
organizational practices as a model that insulates such projects from the
corrupt machinations of election-dependent politicians. Yet there are other
things that New Delhi can do as well to foster the expansion and proliferation
of India’s High Technology sector.
Great floods
have flown from simple sources. - William Shakespeare, "All's Well That Ends Well"
An obvious focus for constructive action is the legal and
regulatory framework under which India’s technology industry struggles daily.
Archaic business regulations and labor laws force Indian high tech firms to
swim thru oceans of red tape and navigate around autocratically imposed
obstacles seemingly designed to thwart companies from making decisions that
would strengthen and grow their enterprises.
This legal miasma is distinctly anti-business and needs to
be gutted or perhaps even discarded wholesale. India’s fabless semiconductor
industry is growing despite this because of the ingenuity and work ethic of
Indian technology professionals. Let those chains be removed so that the sector
can devote its energies to technology innovation and business expansion.
Semiconductors are not the only segment of value to India’s
future in High Tech. The systems and software segments could each add another
deep layer of value that would have widespread positive repercussions across
the domestic economy and ameliorate the nation’s current account deficit. New
Delhi doesn’t even have to actively solicit such corporate investment – there
are global companies already expressing interest in building manufacturing
facilities for system level products in India:
Asus is a giant Taiwanese systems company that designs and
manufactures a vast range of products for the communications, computing and
consumer (3C) markets. A smart move by
New Delhi would be to work closely with Asus and use the engagement as a case
study on what it must do in order to attract more external and internal
investment in High Tech manufacturing.
There is some positive news on this front already. The
cabinet of Narendra Modi already seems to be aware of the issue:
What remains is for the government to more directly address
the legal and regulatory obstacles that are currently impeding the rise of a
domestic systems manufacturing sector.
India’s voting public resoundingly proclaimed its desire for
a healthier business climate to New Delhi in the last election. The new cabinet
and parliament will need to reorient the current practices of government
ministries away from centralized economic governance and management back to their
proper role of serving the people. Stated differently, the goal of New Delhi in
this case should not be to directly impose its authority, but to foster private
enterprise and serve the public interest with a minimal, non-detrimental,
non-interfering presence.
In that vein, subsidies, tax holidays, direct spending and
other kinds of government investment are contra-indicated. Politically-driven
industrial initiatives in democracies are subject to suffering from a lack of
vision, as they are primarily focused on short term effects. Such programs may
lack transparency and are vulnerable to become transformed into pork barrel
funds fed upon by opportunistic crony capitalists. Though ministries may launch
programs with the best of intentions, government bureaucracies frequently lack
the foresight, knowledge and expertise to properly execute useful initiatives
for the high tech sector.
Asus and other sizable international systems companies have
already indicated they are more than willing to spend their own money in order
to establish a local presence in a huge and essentially untapped market. They
are only asking for a compatible business environment in which to set up shop.
The labor force demands of such facilities will also be
highly beneficial to the economy. Factories that produce technically
sophisticated products require a skilled labor force and develop it thru
training, both formally and on the job. Such workers become specialized
craftsmen with intrinsic value in their own right.
A manufacturing plant for cutting edge high tech products
will inevitably attract local Indian semiconductor, subsystem and software talent
around it to found companies that serve the sourcing needs of the facility. In plain
terms, the production facility will spawn its own ecosystem. In the course of
time, this ecosystem will germinate systems companies of its own that will be
more highly attuned to the local market than the foreign manufacturer.
From little
spark may burst a mighty flame. - Dante Alighieri, The Divine Comedy
At this point, it can safely be concluded that the New Delhi
plan to subsidize the construction of semiconductor foundries is misguided and
ultimately disadvantageous to the nation. The more cost effective and
productive approach is the simpler one – to unleash the energy and dynamism of
India’s technology industry and entice foreign investment in high tech
manufacturing by reforming the country’s legal and regulatory structure. The
entrepreneurial spirit of Indians is a natural product of its culture, and the
national economy is like a rich soil that could easily support abundant,
verdant growth – if New Delhi, rather than trying to control it, simply sets it
free.
