Friday, June 13, 2014

Value Proposition and the Custom Chip Market: Part 1 - Overview

As the semiconductor sector enters its Lean era of slow/zero growth and intense price competition, the struggle to attain value, however fleeting its advantage may be in the marketplace, will spell the difference between those who emerge into a new land of plenty and those whose bones lie bleaching in desert wastes. In this new editorial series, we will examine the portion of the chip market that offers customizable logic solutions as their primary value proposition - the ASIC, FPGA and SoC vendors. 

I'm an old hand in custom logic, having started my career with Raytheon Semiconductor in Mountain View, focused on supporting European sales activity for analog ASIC Mil/Aero opportunities (and what a truly weird journey that was  ;-). ) After that, I spent 15 years between IBM & LSI Logic for ASIC and Xilinx & AMD for programmable logic, capping it off with 4 years at MIPS to gain insight from a vendor perspective into the SoC market. As you can readily deduce, the topic of this series is near and dear to my heart, and over time I will be sharing many a war story, tale of woe and amusing anecdote on this blog, derived from my experiences from 20+ years in the business.

For this series, we'll look at a little of the history of each custom logic solution subsegment, how they compare to each other in terms of marketable value propositions, and finally explore potential directions for the future.

Market Requirements & Origins

Where necessity speaks it demands. - Russian proverb

The system level requirements of custom logic solutions are, in some respects, identical to those for any chip a system OEM selects - high levels of 3P optimization, maximum functionality from both hardware & software embedded IP, and board integration specifications regarding pinout, height, airflow conformance & other packaging issues which can be broadly encapsulated by the term 'form factor.' After all, the feature sets of the chips create boundary conditions for the system design team, including board design and cooling requirements.

However, by searching for a semiconductor device that can be personalized for an application, an OEM is indicating that their own end user markets and competitors in those markets are imposing certain uniquely difficult conditions on the system products they create - conditions which inevitably work their way down the value chain as technical requirements imposed on the supplier. These conditions most often exist in OEM markets where at least two of the following factors are applicable:
1. Growth is high. 
2. Complexity is very high.
3. There is no way to collect a set of fixed function chips to solve the design problem at hand without violating at least one of the 3P constraints at the system level.
4. Software content is very high.
5. System product obsolescence is rapid - one year or less.

The requirements these end market conditions generate on a custom logic solution provider include:
1. Facilitating a quick TTM.
2. Ease of Use - both in terms of having the freedom to innovate so that personalization efforts deliver the maximum possible benefit, as well as a design tools suite that offers comprehensive and robust support to the effort.
3. Low Risk - including the ability to deliver on the desired amount of personalization and providing a path whereby design fixes and upgrades can be designed into the customizable chip after the system product's market release.

There is another consideration that, though it steps completely outside the bounds of conventional business issues, is nevertheless a critical one for custom silicon vendors - the 'glamour' factor. Design engineers in High Tech are especially attracted to customizable products. They offer the engineer an avenue for a very individual expression and demonstration of creativity, professional mastery and originality. The results of their endeavors can be both personally satisfying as well as providing an opportunity to show off a bit with their peers in a kind of low key 'macho nerd' display. 

Any supplier attempting to compete in the custom chip sector thus has to pay careful attention to developing products that stimulate the imagination of their target audience, enticing them with the possibilities on offer. At the same time, the customizable solution has to be demonstrably 'safe.' No designer will want to engage with a personalizable chip technology, no matter how personally fascinating he or she might find it, if there is a risk that the solution will fail to deliver on its promises, blow up in his face, harm an end product development schedule and get the engineer in hot water with his boss.

What You Need to Play In The Game

The prerequisites for a chip firm wishing to participate in the custom solutions market are extraordinary. None of the FPGA, ASIC or SoC subsegments covers all these requirements completely, but have each their share of relative strengths and weaknesses. 

A breakdown of the technical parameters of concern to clients of customizable chip solutions is provided below in figure 1.

An explanation is in order here. The grouping of various 'pieces of the puzzle' is only done for convenience and not for weighting the importance of any given factor over another. Stated differently: cost is not necessarily 4x more important than power. In fact, the relative weight of any give puzzle piece is very much dependent on the system design that will employ the custom logic offering. Regardless: system OEMs are looking for all of the above functionality from custom chip solutions, and the more that a given solution can provide, the better the prospects for the vendor.

Furthermore, though a given subsegment of the custom solution sector may offer certain kinds and levels of functionality, how well each vendor in that subsegment supports a given sector capability is individual to each firm. In other words, any measure regarding how well a subsegment covers a given puzzle piece is to be interpreted as a general statement about the subsegment, and may not apply equally to each of its participants.

Now that we've set the parameters for the analysis, we can start looking at the custom logic subsegments individually and see how they stack up against market requirements, as well as how they compare side by side. We'll get into this next week, starting with the ASIC vendors.