Friday, June 12, 2015

Order and Chaos

Battle Between Ravana and Rama in Lanka”, Sahib Din, Udaipur, 1652 (Source:

Chaos, that reigns here
In double night of darkness and of shades. – John Milton, “Comus”

A Plague of Demons

The Ramayana is one of mankind’s oldest extant epic poems. Originally written in Sanskrit, it is a tale of central importance to Indian history, literature and culture. Its verses describe the rise of Ravana, a 10-headed demon and member of the Rakshasa, themselves man-eating demons of insatiable bloodlust, who is nevertheless an extremely learned being and capable ruler. Thru great sacrifices and devotion to Shiva, Ravana is granted boons which bestow upon him almost irresistible might. This near invincibility releases the worst in Ravana, who becomes licentious, cruel, avaricious, aggressive, domineering and arrogant. His ascendancy is such that he extends his dominion over the Devas themselves, becoming a being whose hegemony overshadows the heavens, the earth and the underworld.

The Devas in their anguish approach Vishnu the All-Pervading, Protector and Preserver, and ask for his intercession to end the current state of chaos and restore the cosmos to its natural harmony. To circumvent Ravana’s magical protections, Vishnu manifests himself in his 7th avatar thru the birth of Rama, who upon growing to manhood becomes the king of Ayodhya. 

A living representation of virtue, morality and principled conduct, Rama allies himself with Hanuman, king of the Vanara, and wages terrible war against Ravana and his army of Rakshasa. In the end, Rama slays Ravana, restoring cosmic law and order or dharma to the universe and ruling with righteousness, justice and good works.

The world of High Tech is today wrestling with similarly ferocious demons hiding in the atomic scale limits of silicon below 28nm. What were once 3rd and 4th order effects on physical, electrical and thermal parameters in bulk CMOS that were easily ignored are now 1st order problems that are plaguing designers in their struggles to preserve the 3P (performance, power and price) improvements of Moore’s Law - factors which the semiconductor industry has depended on for the last 4 decades over successively smaller process geometries.

Commercial EDA tool companies have made efforts to keep up with technology progression but have done so blindly throughout their history. Not having their own fabs against which they can verify the latest algorithms coded into their tools, EDA firms have relied on the experience of their customers to identify failings & bugs that can be fixed in post-release patches. The way chip customers typically experience these problems, of course, is from silicon prototypes that don’t work.

Between the licensing & subscription charges for EDA software and the losses incurred in designing and fabricating chips that fail due to faults in those same tools, chip companies have long suffered from the expenses imposed on them by the failings of the EDA sector. The largest chip companies and leading ASIC houses have typically turned to developing their own supplementary tools and utilities to make up for the deficiencies of commercial EDA offerings. However, medium sized companies, small firms and startups simply do not have the resources or finances to spare and have long been competitively hamstrung because of this.

Wards & Protections

Among the firms that have taken their own EDA path is a company whose technology played a dominant role in shaping the 20th century and the second Industrial Revolution - IBM. For over a century now, Big Blue’s primary customers have been Wall Street brokerages, banks and insurance companies – the organizations that constitute the world of High Finance. These clients have shaped IBM both in terms of corporate culture and, more importantly, technology development.

As one might expect, financial firms prize the things they know best and treat certain skillsets with extreme seriousness. One of those is, quite naturally, accounting. For any company in High Finance, absolutely every penny counts – after all, their business is not automobiles, clothing, pharmaceuticals or anything that involves developing and manufacturing things. The financial sector, simply put, is concerned solely and exclusively with money.

It is quite normal for companies such as Morgan Stanley, Wells Fargo or Allstate to handle billions of financial transactions daily. One failing none of them can tolerate is the possibility of accounting errors in automated transaction processing. One can intuitively understand that even losing one penny out of every 1M transactions adds up for such firms.

As a consequence, IBM has traditionally over-engineered its systems and software with fanatical, even maniacal devotion. Software undergoes a testing methodology with a hierarchy of regressions and functionality exercising that borders on clinical psychosis. The worst insult you can deliver to another software engineer in IBM is “your code is lossy.” IBM's hardware is treated with the same extraordinary rigor. SerDes I/O designs with data errors as little as one part per billion are rejected as garbage. Every potential silicon variable is so exhaustively parameterized and characterized that a single flipped bit in an IBM server can be traced all the way down in granularity to an individual defective transistor.

IBM has been capturing the physical and electrical details of its silicon with this level of obsessive thoroughness for over half a century. Many of their EDA tools were developed in-house, maintained and modified as the complexity of design rules grew with each deeper process node and bolstered with comprehensive methodologies for power, performance and cost optimization. As a result, IBM’s servers have historically employed silicon that is considerably faster, cheaper, lower power and more reliable than that available in the rest of the industry.

It was for this reason that IBMers scorned most commercial EDA offerings for so many decades. And now, thanks to a fortuitous turn of events, quite a few more microelectronics designers will be able to do the same.

The Return of Rama

“Ramayana”, Painting on Cotton, author unknown (Source:

Last Monday, IBM announced that it would make a selection of its EDA tools available for general use: 

These tools will be accessible on IBM’s SoftLayer Cloud service thru an interface developed by SiCAD. The interface includes firewalls and data security to allow designers to use the tools and supporting workflows and methodologies on an as-needed basis.

Though a complete chip design from ESL to tapeout cannot be completed with the tool selection, all of the most vital portions of the design flow are supported. IBM has included support for physical synthesis, logic simulation, STA, power analysis, logic verification and SPICE-based analog simulation. Process geometries down to 14nm are supported, including FinFET models.

As is typical of IBM’s attention to excruciating levels of detail to achieve exceptional results, the tools account for the most minute and exotic effects to successful circuit design, including pin capacitance, multiple transmission line models and nonlinear delay effects. A verification testbench, waveform viewer and sophisticated statistical simulation support are also incorporated into the distribution.

Customers do not have to purchase licenses for the tools but can employ them at-will. In order to ensure that customers do not feel that they are being milked for revenue on a time basis, the software is designed to run fast – much faster than similar commercial EDA offerings.

SiCAD partnered with IBM to complete the connection to users and their facilities, setting up and tailoring the environment to customer needs. Users can work using GUI or command line control of the tools. The interface provides workflows for IBM’s design and integration methodologies as well as means of engaging supplementary design services.

“Sed fortuna, quae plurimum potest cum in reliquis rebus tum praecipue in bello, parvis momentis magnas rerum commutationes efficit; ut tum accidit.”
Fortune, which has a great deal of power in other matters but especially in war, can bring about great changes in a situation through very slight forces. – Julius Caesar, “Commentarii De Bello Civili”

The benefits to users are many and far-reaching. Now small SoC companies such as Vitesse and Ikanos can forego a major portion of the expense associated with licensing EDA tools and paying for yearly subscription renewals from Synopsys, Mentor or Cadence. They can also reduce expenses for IT personnel and server hardware, since IBM’s software is on the Cloud. Remaining EDA expenditures can be carefully managed, since the tools are paid for only when used. There are no more updating worries or periodic maintenance fees – the tools available thru the SiCAD interface are kept current. Finally, rather than having to settle for inferior commercial EDA software, small and medium sized chip firms can put themselves on the same footing as the 1st tier semiconductor houses who enhance their own licensed EDA tools with in-house developed utilities.

These, however, are only the directly observable consequences of the event. There are tremendous implications to the long term strategic prospects of chip houses big and small. A major factor blocking 2nd and 3rd tier firms from challenging the 1st tier companies in the ‘major leagues’ has been removed. The competitive playing field has been leveled in the IC industry from a design standpoint, with ominous implications for the likes of Broadcom, Qualcomm, Marvell and other top tier companies, along with likely devastating ramifications for the commercial EDA sector.

Chip design talent can now exert itself without restraint. The reset in competitive dynamics from this seemingly rather slight change will radiate outwards across semiconductors disruptively, generating opportunities for creativity, innovation and growth. The confluence of this event with early stage markets such as the IoT, Robotics and AI will unquestionably see the rise of several Dark Horses over the next decade to once again turn the entire High Technology industry on its head.