Friday, June 27, 2014

Value Proposition and the Custom Chip Market: Part 3 - Programmable Logic

"The Future is Programmable."

The above phrase can be found like a mantra in nearly every executive management slide deck from programmable logic companies for the past three decades. Yet despite the fact that the $5B-$6B programmable logic sector represents less than 2% of the entire semiconductor market, one can still observe statements, positions and behaviors among its participants which suggest a level of obsession with the "righteousness" of programmable technology that would be familiar to members of some fringe religious cult.

So what is it with these PLD outfits anyway? Where did they come from? How did they develop this very peculiar vision of the High Tech world, and where do they appear to be headed for the future?

Today is Yesterday's Pupil. - Benjamin Franklin

To understand programmable logic, it is important to understand the origins of the technology - origins that are still reflected very deeply in its basic makeup. The first attempts at creating bit level programmable functions employed simple memory devices. By manipulating a ROM's data and address lines, one could - hypothetically - create a near infinity of combinatorial configurations. Some of the original silicon companies such as National, Signetics and Texas Instruments based their first programmable products on extant memory architectures and programmed them at the mask level. They also included flip flops on the output pins to support sequential circuits, thus expanding programmable logic from decoding applications into basic state machines.

Monolithic Memories (MMI), a pivotal company in programmable logic's history, arose in the mid to late 70's and made its mark by introducing the first PAL (programmable array logic) - a cascading AND/OR/D-flop architecture that is extremely familiar to all PAL/GAL and CPLD (complex programmable logic device) users today. At first OTP (one time programmable), MMI and other vendors soon moved to EPROM and began incorporating windows over their packaged die so that programmed patterns could be erased in an oven with a UV lamp. 

Granted, this did represent progress, but nobody was particularly pleased with this approach - it took half a day for the device to erase, and depending on the age of the UV lamp, the erasure was not always complete. The sector and its customers breathed a collective sigh of relief once EEPROM-based architectures were developed during the 1980's.

The 80's decade also saw PLD companies move away from Bipolar into bulk CMOS processes. The need for this became glaringly evident to market leader MMI as they experimented with larger bipolar-based arrays and incorporated ECL I/O to drive higher performance. These devices had a nasty tendency to melt and stink up the lab or, on some occasions, produce an entertainingly bright and noisy electric arc and then explode.

The release of AMD's 22V10, MMI's acquisition by AMD and the introduction of the 16V8 by Lattice in the latter half of the 80's also saw the sector move away from Boolean programming to the use of early HDL's such as CUPL, ABEL and PALASM. Throughout the decade, PALs and GALs increasingly gobbled up TTL devices scattered about on PCBs, primarily for the Computing, Communications and Industrial markets. 

Another milestone was achieved in the 80's with the foundation of Xilinx in 1984. A logic cell consisting of a 4 input LUT (lookup table), a D FF and muxes for routing became 'de rigueur' for the most advanced and flexible programmable logic architectures on the market. The regularity and size of the arrays suggested comparisons to their closest hardwired custom logic equivalent, and their SRAM-based configurability naturally led to an appropriate name for the technology - the FPGA (field programmable gate array.) 

Significantly more complex than CPLDs, FPGAs supported more sophisticated sequencers as well as datapath applications, making them particularly well suited for the nascent wireline networking market. Later versions would add many features that lent themselves further to the rapidly growing Communications sector - fast carry chains between logic blocks, hierarchical routing schemes for programmable interconnect, XOR functions, 6 input LUTs, embedded multipliers, high speed I/O including SERDES, hardwired or synthesizable DSPs and CPUs, etc etc. But the guts of the devices were always recognizably faithful to their origins - an SRAM - based lookup table that emulated simple logic functions (in effect, recreating the truth table of that function) supported by a configurable multiplexer scheme.

Ross Freeman's invention of the FPGA was in and of itself a milestone of technical innovation in Silicon Valley history. But the business aspect of the programmable logic market, and eventually the entire semiconductor industry as well, was deeply affected by Ross's partner in the foundation of Xilinx - CEO Bernie Vonderschmidtt, who introduced for the first time in practice the concept and organizational structure of the fabless chip company. Though the long term effects of disconnecting design from manufacturing would not be recognized until much later, the immediate effects to chip firm financials were staggering, as average gross margins of 60% or better became the norm and new product margins of 80-90% became routine in programmable logic. 

With FPGAs, the programmable logic sector began to see itself no longer as the TTL "Pac Man", but as a direct challenger to conventional Gate Arrays and ASICs. This strategic direction began to form just before the first DotCom bubble burst and went into high gear immediately afterwards, as FPGAs became extremely content & feature-rich devices. The EDA aspect of programmable logic solutions also rose to an equal status with hardware, as the increasing size and complexity of FPGAs demanded capable tools support. Xilinx learned this lesson the hard way in 1996 when Altera blew its doors off and surpassed it as market leader solely thru the strength of its tools. Xilinx, however, proved to be a quick learner and returned the favor with a supreme effort on its part, purchasing NeoCAD and undertaking a major internal tools revamp that began to pay dividends in the late 90's and, in conjunction with a series of superior hardware product releases, allowed the company to overtake and then re-establish is dominant 50% market share position in the early 2000's.

The programmable logic sector's conformance to the custom logic 'wish list' is qualitatively illustrated in the figure below.

As one can see from the above 'heat map', programmable logic has made a monumental effort to cover every technical requirement of the custom logic market. However, despite some clear and extraordinary successes, the majority of factors are only partially addressed and the deficiencies are acute.

The most notable thing is the inability of programmable logic to achieve preeminence in any of the three P's. Thanks to high package I/O counts and decent SERDES technology, FPGAs generally do a fair job at supporting the high bandwidth requirements of Communications applications in such functions as protocol interfacing and bridging. However, in terms of raw speed, programmable logic is sorely lacking (except for the tiniest devices.) CPLDs and FPGAs are also notorious power hogs, with Lattice only recently proving the exception with new product families stemming from its acquisition of Silicon Blue. Furthermore, despite efforts by both Xilinx and Altera to provide cost-reduced hardened versions of their arrays for high volume production, their hardwire FPGA programs have proven to be failures. In summary, programmable logic devices are by and large slow, power hungry and expensive devices.

In a supreme effort to position themselves as programmable alternatives to ASICs and SoCs, the leading programmable logic companies have developed an impressive amount of system level IP for their products - often as soft macros, but occasionally as hardened cores. Ironically, however, this has eroded some of the programmable logic advantage in manpower costs versus ASICs and SoCs. It is now a common thing to see anywhere from 10 to 20 engineers working on designs for the largest FPGA chips.

The adoption of CPU and DSP blocks - both as soft cores and hard macros - as well as the incorporation of large multiply-accumulate blocks has turned a great deal of programmable logic engineering attention to software, including DSP algorithms, middleware, operating systems, drivers and API. The dominant firms have also undertaken strenuous efforts to expand their 3rd party ecosystems to help make up for shortcomings with internal software development.

Yet the programmable logic sector has proven itself to be largely unequal to the task. This is understandable, as providing complete support for software stacks across all major market segments - enterprise and carrier networking, storage, wireless infrastructure, automotive, medical, industrial and mil/aero - would be an impossible burden for even the largest semiconductor company. Nevertheless, progress in climbing the learning curve for DSP and CPU technology & applications has been agonizingly slow, and market adoption of these capabilities has been correspondingly gradual.

acta non verba - Motto of the U.S. Merchant Marine Academy ("Deeds, not Words")

The greatest hindrance to much greater growth in programmable logic has paradoxically been their most significant value add - namely, bit level programmability. Deficiencies in the three P's have endured for over thirty years precisely because of a pathological obsession with the "sacred glories" of programmability over the "vile, base world" of the fixed function logic "unbelievers." 

Without question, quite a lot of work has gone into the integration of a multitude of ASIC/SoC-like peripherals, busses and protocol standards. However, the fundamental logic cell architectures for CPLD and FPGA arrays have not strayed far from the path originally set by the 22V10 and the XC 2064. Changes over product generations have been beneficial but nonetheless incremental. In direct contrast to the word-oriented programmable domain of CPU/DSP, architectural innovation in the bit-oriented programmable logic sector has been largely stagnant.

The worst of programmable logic's sins, however, has not been technical, but ethical. The sector grew like a weed during the 1990's and into the first half of the 2000's, and competition was furious. Along the way, PLD companies started to do anything they could possibly do in order to win designs, including the execrable practice of fantastically over-promising and profoundly under-delivering. Pushed remorselessly by executive management, PLD firms routinely practiced gross deception - both to customers and themselves - to the point of cognitive dissonance, convinced that with enough eloquence they could dance their way out of any broken promise. What was worse is that their executive management teams began believing their own B.S. and assumed the preposterous conviction that releasing hardware or software products before they were adequately developed and tested was perfectly OK, as their customers were more than happy to debug those products for them. The FAEs and internal applications support crews, ever brave, stalwart, abused and taken for granted, were left with mopping up these messes and enduring the white hot fury of customers who were repeatedly burned by these disgusting practices.

As a consequence, it became a normal thing for system OEM engineering teams to scoff at anything promised by a PLD vendor regarding product functionality, characteristics and schedules. The resulting deep level of customer cynicism has poisoned the programmable segment of the custom logic market in regard to major innovation.

Yet it is precisely in hardware innovation on which the future of programmable logic depends. When implemented thoughtfully and handled honestly and forthrightly with customers, new hardware architectures do indeed get plenty of traction in the market. Stated differently: if you intelligently try new things and diligently practice what you preach, there is plenty of room for growth in programmable logic.

Lattice has shown the way with its iCE products sourced from the Silicon Blue acquisition. The logic cell is a throwback to the XC2000 days and is arguably even simpler. The architecture is specifically optimized for two of the three P's - price and power. By delivering on the promises they made, Lattice took the low end of the programmable logic segment so swiftly and decisively that its conquest appeared almost unchallenged.

Achronix has cut a brave path thru the wilderness as well with its 22nm Speedster product line. The company was originally founded on an asynchronous architecture that theoretically promised GHz speeds. Unfortunately, this experiment didn't pan out - without synchronization, non-combinatorial designs had an annoying tendency to develop race conditions. As a result, Achronix developed a more conventional programmable array, but integrated a significant number of hardened cores for popular interface and protocol standards - namely, 100G Ethernet, PCIe, Interlaken and DDR3. The result has been a lot more customer interest in this tiny company and the possibility of a 2014 IPO, with Xilinx and Altera doing the rounds in the press in a belated attempt to save face and play catch-up.

Talk not to me of blasphemy, man; I'd strike the sun if it insulted me. - Captain Ahab of Herman Melville's "Moby-Dick"

Why, you may ask, didn't Xilinx and Altera beat Achronix to the punch on this technical direction? Simply because any product proposal that didn't acknowledge the inherent superiority of programmability over fixed function 3P advantages has always been considered "heretical" and "blasphemous." 

The truth is that I am actually one of those propeller-heads who is a diehard fan of programmability. Yet it is clear that the alleged 'maturity' of the programmable logic market proclaimed by pundits is not a function of any inherent sector limitations, but is one of choice, ultimately stemming from a lack of vision. It is an event long overdue for PLD executives to return to reality and recognize that programmability is a very attractive value-adding capability in custom logic, but is nevertheless simply one of many, and that mastering the custom logic market will mean mastering all of its technical demands.

The final sector of the custom logic market - the SoC vendors - has done a much better job of placing programmability in an appropriate context, as we shall see in the next installment of the series.


  1. The final sector of the custom logic market - the SoC vendors - has done a much better job of placing programmability in an appropriate context...

    You should look at the NXP LPC812. "Any pin, any function" - not quite - but very close.

    Or the GreenArrarys GA144 - which is all "software" and not much hardware - instead of the LUT a microprocessor is the base function. You get 144 of them.

    1. What is your take on those devices, Simon? Where do they 'fit', so to speak?

  2. I LOVE the '812. I wish NXP made a version with more pins ans a second I2C port. Board layout is eased greatly and each pin has a number of functions to choose from. I use them like glue logic. Assuming I don't need high speeds. Things like a USB (serial actually) to I2C converter. Or SPI to I2C. That is handy for environmental sensing.

    The GA144 is on the right track. Its programming model is a little strange (Forth) but I'm familiar with that (actually I love it). Three things I'd like for the processors - a longer word length. 18 bits seems to get people off track. 32 might be better. But that is minor - what it really needs is more CPU memory RAM and Flash programming of the ROM. But I'd just settle for more CPU memory RAM.

  3. Consolidation is inevitable in the PLD space. The glory days of hyperbolic growth are over and has given way to the largest of these companies becoming cash cows and will be treated as such.


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